Modelling IP & Methodology

We provide re-usable modelling methodology, that helps the customers to get started quickly with their modelling projects.

CircuitSutra Modelling Library (CSTML)

CSTML is a library built on top of SystemC & TLM2.0. This library is a collection of convenience classes and utilities that ease the model development activity for virtual prototyping.  It comes with IP-XACT compliant register implementation, Model generator utility, Lua based configuration at different levels of hierarchy, Advanced error messaging built on top of sc_report, Python based unit testing framework, and various other useful features.

Virtual Prototype – Quick Start Package

Library of basic models and modeling infrastructure that can be used to quickly start a virtual prototype project. Re-usable modeling infrastructure for specific communication interface or specific application domain

Transaction Level Implementation for specific communication interfaces

  • UART, SPI, I2C, Ethernet, USB, MMCSD, LPDDR, HBM, Camera, Display, ..
  • TLM protocol and convenience sockets
  • Sample models, Traffic generators, Traffic monitors
  • Backend modeling infrastructure to access the host computer interfaces in the Virtual Prototype
  • Can be used to quickly develop the models of IP complaint with the communication interface
  • Modeling engineers need not worry about modeling the complex communication protocol at transaction level.  They can focus on implementing their IP specific registers and call the API of these sockets to initiate the communication
  • Significantly  reduce the efforts to develop the IP models compliant with these communication protocols and effectively use them in the Virtual Prototypes

CPU Modelling Framework

CST-ISS: A generic framework for Instruction Set Simulator (ISS)

  • Architecture Independent framework: ARM, RISC-V, Any other ..
  • Use any ISS in plug & play fashion in the SystemC Virtual Platform
  • Develop your own custom CPU Model quickly  by leveraging re-usable features
  • Use multiple ISS as reference for the fool proof verification of your CPU RTL
  • Common Features:
    • SystemC/TLM2.0 Integration. Extensible to integrate with any other simulation environment
    • Integration with GDB, Debug Tools, IDE
    • Tracing (RISCV N-Trace & Other formats)
    • Semi-hosting
    • External Debug Support (compliant to RISCV Debug Specification)
    • Command Line Arguments, Configurability
    • Running simulation in 32 / 64-bit mode

Modelling Methodology for RISC-V Ecosystem

There are several Open-Source Instruction Set Simulators (ISS) available for RISC-V: Spike ISS, VeeR ISS from ChipsAlliance, MPACT-riscv from Google, Whisper ISS from Tenstorrent, QEMU.

Each of these have some pros / cons in terms of feature availability, quality, performance etc.. Difficult to use these in the SystemC and other simulation environment Difficult to integrate with debug / analysis tools

For RISC-V we have an innovative CPU modelling framework that allows the use of any open source instruction set simulator (ISS) seamlessly into the SystemC virtual prototype or other HDL simulation environment. It also enables the customers to develop their own custom ISS quickly by leveraging the common features. 

It comes bundled with the virtual platform of a reference SoC, and can be used as the starting point to develop the virtual platform of a customer’s specific SoC. 

We are extending the modelling framework for performance modelling of RISC-V CPU

Reference Virtual Prototype

Virtual Prototype of Core-V-MCU: An Open Source SoC from OpenHW foundation

Register Accurate, Loosely timed model 

Developed using CircuitSutra Modelling Methodology (CSTML, VP-QSP)

Primary Use Case:

  • Pre-silicon software development
  • CI/CD flow for automated testing of firmware

Abstraction

  • Timing Abstraction: Removed the clocks
  • Interface Abstraction: Transactions instead of pins
    • TLM2.0 for memory & register access
    • Custom TLM for: UART, QSPI, I2C, SDIO, etc..
  • Functionality Abstraction: Implemented only what is visible to software

     

CPU Model: CST-ISS 

eFPGA: Implemented as a stub model

Further extend for: Co-simulation & Hybrid

  • SW driven verification of RTL, HW-SW partitioning

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