Architecture models are used for the early exploration of SoC architecture, conduct the performance / power analysis on real work loads and optimize the architecture for specific target applications. These are mainly cycle accurate / cycle approximate transaction level models. Abstraction must be chosen wisely so that bottlenecks in the architecture can be identified.
Cycle Accurate Transaction Level Model (CA-TLM) are required for the communication protocols, interconnects, memory subsystems etc.. These models have sufficient timing accuracy required for the purpose of performance analysis, and still significantly faster compared to RTL.