The SystemC models developed at different abstraction levels may be combined together in the same simulation using the adaptors. Loosely timed transaction level models can be combined with the cycle accurate transaction level models or the pin accurate models by developing appropriate adaptors.
The higher abstraction level SystemC models / virtual platforms may be combined with the RTL simulation / emulation.
Such advanced, hybrid flows can be used to progressively validate the functionality of the RTL blocks using the software driven test cases. These can also be used to validate the higher abstraction models / virtual platforms using the SystemVerilog/UVM based RTL verification setups.