Chip designing at Higher Level of Abstraction – Above RTL using high level languages: Synthesizable subset of C, C++, SystemC
Fast, High-Quality path to RTL
5 – 10x Less Code: Reduce design efforts
10 – 1000x Faster Simulation: Increased productivity
Multiple implementations from same input source
- Tech Library: FPGA / eFPGA / ASIC / Different tech nodes
- Directives/Constraints: Optimize Power / Performance / Area
Bridges Hardware & Software Domain
- Opens the use of FPGAs to embedded software engineers
- Vast pool of free C / C++ tools available to designers
- Existing C / C++ implementations available to start with