Architectural & Performance Modeling

We support our customers to develop the models and modeling infrastructure for Architecture exploration and Performance analysis of multicore SoC and electronics systems.

The models are developing using C / C++, SystemC

We have exposure to the following activities in various customer projects:
  • Cycle accurate and Cycle approximate TLM models of SoC bus, NoC, Cache coherent interconnect
  • Models of Memory controllers, Memory sub system, Cache, MMU
  • Using GEM5 simulator

CircuitSutra have also defined a methodology for Architecture & Performance modeling. Following are the various elements of the methodology.