QEMU based CPU models with SystemC / TLM2.0 interface

CircuitSutra has expertise to use the processor model from QEMU in the SystemC based virtual platforms. We extract the CPU model portion from the QEMU code base and create the SystemC / TLM2.0 wrapper on top of this. We have also added various useful features to enable the debug & analysis of SW running on virtual prototypes.

Features:
  • Can be used in SystemC / TLM2.0 based virtual prototype
  • Provides an API to load the binary / elf file
  • Option to generate the trace
    • Instruction trace
    • Register trace
    • Lists the skipped & taken instructions in the IT block
    • Lists the conditional branch instructions (condition pass / fail)
  • Can be integrated with the debugger
    • Ddd
    • Eclipse
    • Any GDB compliant debugger
  • User can specify which address space is outside of CPU model and which address space is inside the CPU model
    • This allows some of the system components to be used from with QEMU (NVIC etc.. ), instead of modeling these in SystemC