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SystemC based
SoC Modeling Services
SystemC
has the potential to change how the chips are designed and how the
embedded software is developed. The SystemC / TLM based design and
verification flow can raise the abstraction of chip design and provide
the long awaited productivity gains to tackle the ever growing
complexity in chip design process.
With strong focus on
SoC modeling, CircuitSutra is all set to play an
important role in the future of Semiconductor industry.
Virtual Platform
for embedded software development
- Allows the embedded software development without FPGA board
- Chip design and eSW can proceed in parallel. Reduces TTM
for SoC
- Advanced tools are being available for better eSW
development and debugging
Synthesizable
models for High Level Synthesis (HLS)
- High level design using Synthesizable SystemC Subset
- Designer can focus on implementing the functionality
- HLS tools can generate the most optimum RTL code for
specific constraints
- Power, Area, performance
constraints
- Process node
- Process node
- Raises the abstraction of chip design
- SystemC might replace verilog as the language of chip design
SystemC models
for RTL verification or HW/SW coverification
Bus specific TLM
kit by extending OSCI TLM2.0
SystemC-AMS:
Virtual models of analog & mixed signal blocks
Modeling Standards supported
CircuitSutra
is a strong supporter of STANDARDS. The models that we create can be
integrated into any ESL / EDA environment without requiring any change
in the models, this is a necessary condition for SystemC to become the
language of choice for design entry. CircuitSutra is highly commited to
enable the widespread adoption of SoC modeling standards in the
industry.
- SystemC IEEE 1666
- OSCI TLM2.0
- STARC TL Guidelines V2
- OSCI Synthesizable SystemC subset
- OSCI SystemC-AMS
- OSCI CCI (participating in the working group)
- OCP-IP TLM Kit
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